in the framework of the 37th Annual IEEE/IFIP Int. Conf.
on Dependable Systems and Networks (DSN-2008) —
Friday June 27, 2008 — Anchorage, AK, USA
Submission deadline : March 7, 2008
Author notification : April 11, 2008
Camera ready copy : May 2, 2008
Motivation and Theme
Unprecedented levels of information processing, novel architectural
solutions and a new realm of applications promise to be reached thanks to the advances in semiconductor technologies for integrating extremely large numbers of transistors or processing elements into a chip. Towards this ends, two main tracks are being considered :
o Top-down "More Moore" : this track is pushing further the long standing Moore¹s Law-based trend in chip development that aims at reducing the dimensions of silicon microelectronics and is progressively reaching nanometric scale elementary devices.
o Bottom-up "More than Moore" : this track features atomic assemblies
of nanoscale technologies ; these include nanowires, carbon nanotubes
or organic molecules, etc., and extend also to quantum computing,
optical computing and micro/nanofluidics.
Due to the differences in relative advances and current industrial concerns attached to each track, this second edition of the Workshop still plans to emphasize the top-down track for which it is widely recognized such an evolution raises serious challenges both from the Dependability and Security viewpoints. Nevertheless, considerations attached to the above mentioned emerging nanoscale technologies are also part of the scope of the Workshop. Indeed, such technologies are intrinsically exposed to a significant rate of residual defects and fault occurrence and < to some extent < reminds the early days of digital computers and relate to the seminal work then developed to improve their reliability.
The long standing Moore¹s Law-based trend in IC development is aiming at nanometric scale elementary devices. Such technologies are already impaired by significant variations affecting process parameters and thus become a nightmare to reliability engineers for reaching an acceptable manufacturing yield at viable cost. The dramatic reduction of digital evices is accompanied by a decrease in power supply and threshold levels which in turn results in lower noise immunity and greater exposure to particles. Moreover, additional instabilities may affect circuit parameters in operation, e.g., in CMOS devices negative bias temperature instability (NBTI) has a strong impact on threshold voltage over time.
Examples of vulnerabilities and malicious threats related to hardware chips are information leakages attached to side channels attacks or differential fault analysis based on applying environmental disturbances or even fault injection. Device downsizing and increased chip complexity are commonly understood as positive factors in reducing hardware vulnerabilities with respect to security issues (especially for what concerns cryptochips or IC intellectual property). Nevertheless, one should not neglect the related problems attached to the observability and controllability facilities provided by scan-based testing devices incorporated into the chips.
Scope and Objectives
The Workshop is aimed at characterizing these impairments and threats as well as distinguishing possible alternative design approaches and operation control paradigms that have to be enforced and/or favored in order to keep achieving dependable and secure computing. Three main goals were identified for the Workshop :
o Review the state-of-knowledge concerning the threats at stake in nanocomputing technologies : manufacturing defects, accidental operational faults, malicious attacks.
o Identify existing solutions and propose new solutions attached to various design options for mitigating faults and implementing secure and resilient computing devices and systems.
o Forecast the risks associated to emerging technologies and foster new trends for cooperative work, possibly combining various alternatives to help increase the pace of advances and solutions.
Participation, Submission and Selection Process
The workshop is open to all researchers, system developers and users who are involved with or have an interest in dependability and security of hardware technologies. We are interested in submissions from both industry and academia on all topics related to dependable and secure nanocomputing. Potential topics of interest include, but are not limited to : failure modes and risk assessment, yield and mitigation techniques in nanoscale technologies, on-line adaptive and reconfigurable nanoarchitectures, design techniques for developing resilient nanosystems, fault-tolerant architectures specific to nanoscale circuits, scalable verification and testing methodologies, network on chip and communication protocols, etc.
All prospective contributors should submit an extended abstract,
work-in-progress report or position paper. Submissions must be original work with no substantial overlap with previously published papers or simultaneous submissions to a journal or conference with proceedings. The submissions should conform to the proceedings publication format (IEEE Conference style) and should not exceed six pages (including all text, references, appendices, and figures). They should explain the contribution to the field and the novelty of the work, making clear the current status of the work. Each submission should start with a title, a short abstract, and names and contact information of the authors. Submissions will be fully refereed by three PC members. Accepted papers will be published in a supplement volume of the DSN 2008 proceedings. Authors of accepted papers must guarantee that their paper will be presented at the workshop.
Submissions must be made electronically (in PDF format), preferably via the Workshop Webpage. The organizers can be reached by e-mail at : dsn2008-nanocomputing[at]laas.fr.
o Jean Arlat, LAAS-CNRS, Toulouse, France
o Cristian Constantinescu, AMD, Fort Collins, CO, USA
o Ravishankar K. Iyer, UIUC, Urbana-Champaign, USA
o Michael Nicolaïdis, TIMA, Grenoble, France